The present invention generally relates to computer systems and, in particular, to a signal comparison system and method for improving data analysis by analyzing transitions of a data signal with respect to transitions of a clock signal and by adjusting the timing of the data signal and/or clock signal transitions to correct for timing errors.
As known in the art, data within a computer system is typically sampled with respect to a system clock signal. For example, a data signal may be sampled at the occurrence of every rising edge and/or falling edge of a clock signal When the data signal is synchronized with respect to the clock signal, the clock signal is designed to produce one sample for each bit of the data signal (e.g., a clocking edge of the clock signal occurs once for every bit of the data signal). Accordingly, each bit of the data signal is reliably sampled and used by the computer system to perform various functionality.
Ideally, transitions of the clock signal do not occur close to transitions of the data signal. If a data signal transitions too close to the occurrence of a clock transition, then the data may be in a transition state when the data signal is sampled, thereby causing the data to be unreliable. Furthermore, small timing variations can cause the clock transition to actually skip a bit of data and to prematurely sample the next bit of data. Therefore, great care is usually taken to keep transitions of clock signals sufficiently separated from transitions of data signals in order to ensure data reliability.
Unfortunately, sufficient separation of data signal transitions and clock signal transitions cannot always be ensured. Errors in generating data signals and clock signals as well as delays in processing data signals and clock signals cause the transitions of the two signals to fluctuate with respect to one another such that data signal transitions may occur too close to clock signal transitions to ensure reliable data. Therefore, there exists a need for a system or method for determining when data signal transitions occur with respect to clock signal transitions and for adjusting the transitions of the data or clock signal when the transitions of the two signals are too close. This is especially true in systems that receive data signals and clock signals from external sources such as logic analyzers, for example.
Logic analyzers analyze data generated within an external computer system or other digital system in order to determine errors within the data. Therefore, logic analyzers receive data from the system under analysis and sample the data relative to an external clock signal also received from the system. It is desirable for the logic analyzer to ensure that transitions of the received clock signal are not occurring too close to transitions of the received data signal. Otherwise, timing errors could occur that corrupt the analysis of the data.
Many prior art systems test for adequate separation of data signal transitions and clock signal transitions by having the system under analysis transmit a predetermined data signal for calibration. In this regard, the sampled data is compared to the predetermined data to determine whether the two match. If the two data signals match, then it is assumed that there is adequate separation of the transitions of the data and clock signals However, if the two data signals do not match, then the timing of the two signals is adjusted, and the data is then retested. This process is continued until the two signals match.
Not only does this prior art method take time to establish an accurate result, but the system under analysis must be able to generate a xe2x80x9cknown-goodxe2x80x9d signal. Furthermore, the timing of the clock signal transitions with respect to the data signal transitions is not actually determined, making it difficult to isolate the source and amount of error when the two data signals do not match.
Thus, a heretofore unaddressed need exists in the industry for providing a signal comparing system and method for determining transitions of a data signal relative to transitions of a clock signal and for adjusting the timing of the transitions to prevent timing errors. Furthermore, the enabling mechanism 97 should be configured to enable the timing of the clock signal 12 or the data signal 14 to be adjusted relative to the other signal 12 or 14 only during time periods after each of the latches 74-49 has received the same transition of the data signal 14 and before any of the latches 74-49 has received the next transition of the data signal 14.
The present invention overcomes the inadequacies and deficiencies of the prior art as discussed herein. The present invention provides a system and method for improving data communications by determining when transitions of a first signal occur with respect to transitions of a second signal and by adjusting, when appropriate, the transitions of the two signals.
The present invention utilizes a first latch, a second latch, a third latch, a first delay mechanism, a second delay mechanism, and a feedback mechanism. Each of the latches receives a first signal and a second signal and transmits a respective value of the first signal in response to a transition of the second signal. The first delay mechanism delays the transition of the second signal before the transition is received by the first latch, and the second delay mechanism delays the transition of the second signal before the transition is received by the second latch. The feedback mechanism receives the values transmitted by the latches and determines whether these values are logically equivalent. The feedback mechanism then transmits a feedback signal in response to a determination that one of the values is logically different than another of the values.
In accordance with another feature of the present invention, a third delay mechanism delays the first signal and adjusts the delay of the first signal based on the feedback signal transmitted by the feedback mechanism.
In accordance with another feature of the present invention, an enabling mechanism transmits an enabling signal to the third delay mechanism after the transition of the second signal has been received by each of the latches and before the next transition of the clock signal is received by any of the latches.
The present invention can also be viewed as providing a method for correcting timing errors. Briefly described, the method can be broadly conceptualized by the following steps: receiving a first signal and a second signal; latching a value of the first signal in response to a transition of the second signal; latching another value of the first signal in response to the transition of the second signal; delaying the transition prior to one of the latching steps; comparing the values; transmitting a feedback signal based on the values; and adjusting a delay of the first signal based on the feedback signal.